1. Field of the Invention
The present invention relates to a rewritable non-volatile semiconductor memory device.
2. Description of the Related Art
As are well known in the art, EPROMs (Erasable Programmable Read-Only Memory), EEPROMs (Electrically Erasable Programmable Read-Only Memory), and the like, represent non-volatile semiconductor memory devices into which a user can rewrite data.
In the case of an EPROM, data is written using a writing element called a programmer (or a writer). In an EPROM, UV light is used to collectively erase data stored in the entire array of memory cells.
Each memory cell of an EPROM may be made from a transistor, which reduces the area of the memory cells. This is advantageous in that integration of a mass storage device becomes easy and a bit unit price may be reduced.
However, since data in an EPROM is erased by radiating UV light onto the chip, a ceramic package using expensive quartz glass is required. This limits possible reduction in the chip unit price. Moreover, since data is written by a dedicated writing device (e.g., a programmer, or a writer), an EPROM needs to be installed on a board via a chip-detachable socket. This enables the chip (i.e., EPROM) to be detached in order for the data to be written thereto and thereafter re-attached to the socket. This is not only troublesome but also undesirable in view of cost required for chip installation.
An EEPROM, on the other hand, is desirable in that data can be written and erased while the EEPROM is installed on a board. However, in order to enable writing and erasing, for example, at a bit level, a select transistor is required for each memory cell to enable the memory cell to be selected. Thus, the area required for each memory cell of an EEPROM is about 1.5 to 2 times larger than that of a memory cell in an EPROM. Accordingly, a bit unit price of an EEPROM is increased as compared to an EPROM. An EEPROM is therefore less desirable for application as a mass storage device.
A flash memory has been proposed as a non-volatile semiconductor memory device having advantages of both an EPROM and an EEPROM. A memory cell of a flash memory is disclosed, for example, in U.S. Pat. No. 4,949,158. FIG. 9 is a schematic diagram showing the structure of a memory cell within the flash memory. As shown in FIG. 9, the memory cell according to U.S. Pat. No. 4,949,158 is a floating-gate-type FET (Field Effect Transistor) which is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which a control gate CG is provided on a gate oxide film, with a floating gate FG being provided in the gate oxide film.
In the above-described flash memory, each memory cell is made from one transistor without any select transistor, and a plurality of memory cells are collectively erased at a chip level or at a block level. Accordingly, a bit unit price of the flash memory can be reduced as low as that of an EPROM and the flash memory is applicable as a mass storage device. Furthermore, in the same manner as an EEPROM, data can be written to and erased from the flash memory without detaching the chip from the board. In addition, since no UV light irradiation is required, an inexpensive plastic package can be used.
Generally, a NOR type flash memory and a NAND type flash memory are used. In the NOR type flash memory, transistors of memory cells (hereinafter, simply referred to as "cell transistors") are individually connected to a bit line. In a NAND type flash memory, a plurality of serially connected cell transistors are collectively connected to a bit line. Accordingly, the NAND type flash memory requires small connection areas between the bit line and the cell transistors, and thus the areas of the memory cells can be reduced. However, the access speed for reading data by random access is decreased. Other than the NOR and the NAND flash memories, there are, for example, an AND type and a DINOR type flash memory. In these AND type and DINOR type flash memories, processes of injecting electrons into and removing electrons from the floating gate FG during erase and write operations are opposite to those processes in the NOR and NAND type flash memories. For this reason, hereinafter, only NOR and NAND type flash memories will be described as examples.
In the above-described flash memories, the presence or absence of electrons within the floating gate represents data of "0" or "1".
In order to read data from each cell transistor of the flash memory, a power-supply voltage Vcc (usually about 5 V) is applied to the control gate CG while the source S is grounded (0 V) and a low voltage of about 1 V is applied to the drain D. In the case where no electrons are stored in the floating gate FG, a threshold value of the cell transistor is low such that a drain current (a channel current) flows between the drain D and the source S. In the case where electrons are stored in the floating gate FG, a threshold value of the cell transistor is high such that no drain current flows between the drain D and the source S. Accordingly, data stored in the cell transistor can be read out by detecting the magnitude of the drain current.
Hereinafter, data "0" refers to a state where the threshold value is high because electrons are stored in the floating gate FG, and data "1" refers to a state where the threshold value is low because no electrons are stored in the floating gate FG.
In reading data from the cell transistors, as described above, the voltage applied to the drain D is as low as about 1 V. Otherwise, an application of a high voltage induces undesirable parasitic weak write (soft write).
In order to erase data stored in each cell transistor of the flash memory, a high voltage of about 12 V is applied to the source S while the control gate CG is grounded. By doing so, a high electric field is generated between the floating gate FG and the source S, whereby electrons stored in the floating gate FG are removed as a tunnel current through the thin gate oxide film. Accordingly, a threshold voltage of the cell transistor is reduced, whereby the cell transistor is initialized to a state where data "1" is stored, i.e., data is erased. Such erasing of data is collectively performed on the cell transistors at a chip level or at a block level.
In order to erase data by applying a high voltage to the source S as described above, a withstand level of the source junction with respect to an applied voltage must be increased. This causes some disadvantages. For example, forming fine voltage supply lines that extend to source electrodes becomes difficult, or hot holes generated in the vicinity of the source junctions may be partially trapped in the gate oxide films, thereby deteriorating the reliability of the cell transistors.
In a method for erasing data which has overcome the above-described problem, a power-supply voltage Vcc (usually about 5 V) is applied to the source S while applying a negative voltage of about -10 V to the control gate CG so as to remove the electrons stored in the floating gate FG as a tunnel current (hereinafter, the method is referred to as "a negative gate erase method"). According to the negative gate erase method, a voltage applied to the source S is sufficiently low for the withstand level of the source junction with respect to an applied voltage to be low, and thus gate lengths of the cell transistors may be reduced.
Furthermore, according to a method where a high voltage is applied to the source S, a tunnel current that flows through the cell transistor at the time of erasing data may reach a total of several milliamps (mA) for the entire chip. Since a step-up circuit integrated in the chip has a very small current supply ability, a sufficiently high voltage cannot be supplied. Therefore, not only the power-supply voltage Vcc but also the high voltage used for erasing data needs to be supplied from an external power source. On the other hand, according to the negative gate erase method, a power-supply voltage Vcc is sufficient as a voltage applied to the source S, and thus, a high voltage is not necessary.
After erasing data stored in the cell transistors as described above, data is written into the cell transistors. In writing data into each cell transistor, a high voltage of about 12 V is applied to the control gate CG while the source S is grounded and a voltage of about 7 V is applied to the drain D. Accordingly, a large current flows between the drain D and the source S, and hot electrons with high energy generated in the vicinity of the drain junction are injected in the floating gate FG, whereby electrons are stored, i.e., data "0" is stored.
According to the above-described write operation, only the initialized data "1" is rewritten as data "0" and data "0" cannot be rewritten as data "1". Therefore, in a flash memory, an erase operation is performed to the cell transistors prior to a rewrite operation. In other words, all of the cell transistors in the chip or the block are initialized once, after which cell transistors are selected and data "0" is stored in the selected cell transistors.
In order to inject electrons into the floating gates FG by utilizing hot electrons as described above, a large current of about 1 mA needs to be supplied to each cell transistor at the time of writing. Regarding this fact, a flash memory has been developed which operates in the same manner as an EEPROM, where electrons are injected by utilizing a Fowler-Nordheim (FN) tunnel current, thereby reducing a current required at the time of writing. Accordingly, the power source is simplified in this flash memory.
In each cell transistor of a flash memory, a write operation is performed on a drain junction side and erase operation is performed on a source junction side. Accordingly, in designing the device, it is preferable that each of the junction profiles be individually optimized in accordance with their respective operations. Specifically, a field-concentration-type junction profile is applied to the drain junction so that write efficiency is enhanced, whereas a field-relaxed-type junction profile is applied to the source junction so that a high voltage is applicable at the time of erasing, whereby the drain junction profile and the source junction profile being asymmetrical.
In view of recent portable electronic apparatuses designed to operate using battery power source, or in view of the desirability of producing reduced-size semiconductors, there has been a need for a semiconductor device which can operate with a lower voltage. In order to meet such a demand, semiconductor devices in which a power-supply voltage Vcc is reduced from 5 V to 3.3 V have been vigorously developed. Accordingly, flash memories which are operable with a power source of 3.3 V have also been developed. At present, however, even in a flash memory employing a power source of 3.3 V, a voltage applied to the control gates CG of the cell transistors is supplied by stepping up a power-supply voltage Vcc from 3.3 V to 5 V by a word line step-up circuit integrated on the chip, in order to ensure high speed operation and sufficient operation margin.
The flash memory differs from RAM (Random Access Memory) in that it is capable of selectively setting various operation states such as writing and reading data, collectively erasing a plurality of memory cells at a chip level or at a block level, and reading out from a status register. In the case where these operation states are to be specified by a combination of external control signals such as a chip enable signal /CE, a write enable signal /WE, an output enable signal /OE, or the like, the number of types of control signals need to be increased compared with available EPROMs or EEPROMs. In this case, since additional input terminals are required for the corresponding control signals, the input terminals of the flash memory are no longer compatible with those of the EPROM, EEPROM or the like, thereby rendering the device less usable. Thus, according to a major command system of an actual flash memory, instead of inputting the combinations of control signals, combinations of data or addresses are input as various commands for specifying various operation states. In this case, the flash memory is provided with a command state machine (CSM) for determining each of the various externally input commands, and a write state machine (WSM) for executing the determined command.
Furthermore, the above-described flash memory in which an erase operation is performed at a block level may include blocks of various sizes or blocks of equal sizes (U.S. Pat. No. 4,945,570).
In addition, there is a flash memory in which each block is provided with a BP (Block Protect) data memory region. BP data which inhibits erase and write operations of data in the block is stored so as to protect data in the block. In this particular flash memory, /WP (Write Protect) input terminals are provided to which /WP signals are externally input. When the /WP signal is active (low), BP data in each block is validated. When the /WP signal is inactive (high), BP data in each block is invalidated. Thus, in the case where an active (low) /WP signal is input into the /WP input terminal, when BP data is stored in the BP data memory region, erase and write operations to the block are inhibited, and when BP data is not stored in the BP data memory region, erase and write operations to the block are allowed. In the case where an inactive (high) /WP signal is input into the /WP input terminal, erase and write operations to the block are allowed regardless of the presence of BP data in the BP data memory region of the block.
Instead of providing /WP input terminals, a WP setting command and a WP releasing command may be used, in which case there is no need for increasing the number of the input terminals. Specifically, when a WP setting command is input to a flash memory employing the above-described command system, a /WP signal stored in the flash memory is activated (low). When a WP releasing command is input to the flash memory employing the above-described command system, a /WP signal is inactivated (high). In this manner, the BP data in the BP data memory region is either validated or invalidated. Since /WP input terminals are not necessary in this case, compatibility between input terminals of the flash memory and input terminals of an EPROM, EEPROM or the like is maintained.
However, cell transistors of a flash memory may be in an excessive erase state where electrons are excessively removed from floating gates FG during the course of an erase operation, whereby a threshold value of the cell transistor becomes a negative voltage. Since select transistors are omitted in the cell transistors, when the threshold value of the cell transistor becomes a negative voltage during the course of the erase operation, a leakage current is generated in non-selected cell transistors which share the same bit line as the selected cell transistors during the course of a read operation. As a result, data stored in the selected cell transistors is not accurately read out, which results in a critical defect.
In order to prevent such an excessive erase in such a flash memory, a pre-write operation (Program Before Erase) is performed which provides electrons, i.e., which writes data "0", beforehand in a floating gate FG of each cell transistor which is to be subjected to an erase operation, thereby standardizing the amount of electrons in the floating gates FG of all of the cell transistors. Accordingly, in an erase operation following the above-described pre-write operation, electrons stored in the floating gates FG of all of the cell transistors are equally removed, thereby preventing electrons from being excessively removed from floating gates FG of only some of the cell transistors.
In an erase operation, after a short period of erase process, whether or not the erase process has completed is confirmed by an erase verification. The short period of erase process and erase verification are repeated until data in all of the cell transistors are completely erased. According to the above-described method, unnecessary removal of electrons from the floating gates FG of the cell transistors is prevented.
In the above-described flash memory, however, a significantly long period of time (e.g., several hundreds of milliseconds) is required for erasing data in every cell transistor. Thus, a probability of a power source being cut-off or a reset signal being received during an erase operation is increased during this long erase operation. The erase operation may be forcibly terminated as a result, and the probability of this occurring is not negligible.
When an erase operation of a cell transistor is terminated for some abnormal reason, not all of the data in the cell transistor is initialized as data "1" (where a threshold value of the cell transistor is small) and a part of data in the cell transistors will remain as data "0" (where a threshold value of the cell transistor is large). Since a write operation is only capable of rewriting initialized data "1" as data "0" as is described above, data "1" is written by remaining the initialized data "1" unchanged. Thus, when data of the cell transistors partially remain as data "0" after the erase operation, data "1" cannot be written into such cell transistors.
For this reason, the flash memory is troublesome in that a possibility of data not being completely erased for all cell transistors is a concern. This complicates programming of a system incorporating the flash memory.
Alternatively, there is a flash memory which is provided with a status register for storing a bit representing whether or not the erase operation has succeeded.
However, when the erase operation is forcibly terminated due to the cut-off of the power source or a reset of the device, the status register is reset as well. Thus, whether or not the erase operation has been successful is no longer confirmed by the register in such situation.
A counter measure against the above-described forcible termination of the erase operation is disclosed in Japanese Laid-Open Publication No. 5-325577. FIG. 10 is a block diagram showing a flash memory device according to this conventional method. Referring to FIG. 10, a flash memory card 101 includes an I/O port 102, a power control section 103, a terminal control section 104, an address latch section 105, an address control section 106, first to eighth flash memory ICs 107a to 107h, a data bus 108 connected between the I/O port 102 and each of the flash memory ICs 107a to 107h, and an address bus 109 connected between the address control section 106 and each of the flash memory ICs 107a to 107h.
In the flash memory card 101, when data stored in the first flash memory IC 107a is erased, data "0" as a flash memory IC erase complete information is written into a flash memory card final address (i.e., an erase area recording region). Furthermore, when data stored in the second flash memory IC 107b is erased, data "0" as a flash memory IC erase complete information is written into an address preceding the flash memory card final address (i.e., the erase area recording region). This process is repeated for every erase operation of the flash memory ICs 107a to 107h.
According to the above-described method, the erase complete information is 1 bit. When the erase operation is forcibly terminated due to cut-off of the power source or a reset of the device (in other words, when sequential processes of pre-writing data as "0" and initializing the pre-written data as "1" are forcibly terminated), the erase complete information cannot be specified as data "0" or "1". In this case, whether or not the erase operation has been successful cannot be confirmed.
Therefore, when the erase operation is forcibly terminated due to the cut-off of the power source or reset of the device, for example, the only way to confirm whether or not data has been successfully erased is to read out data from every cell transistor one-by-one. Since data "0" is no longer writable, the write operation should not be continued and thus additional error operation is required, thereby complicating programming of a system incorporating the flash memory.